The present invention relates to improvement of multilayer routing method and structure for a semiconductor integrated circuit.
Recently, the development of the technique in the field of semiconductor integrated circuits can provide a semiconductor integrated circuit including several million transistors mounted on merely one chip. For the purpose of decrease of the production cost of a semiconductor integrated circuit, it is necessary to further minimize the size of a semiconductor LSI chip, namely, to lay out at a high density a plurality of unit circuits (i.e., functional blocks or cells) and wires for logically interconnecting the unit circuits with-one another. From this point of view, the layout design for a semiconductor integrated circuit plays a significant role.
In the conventional layout, two-layer metal (aluminum) routing was regarded as a leading technique, but the recent technical development can now attain multilayer routing using three or more layers. An example of techniques for supporting the multilayer routing includes CMP (chemical metal polishing) method. The CMP method is a technique to flatten layers by polishing. Owing to this method, a plurality of layers can be uniformly stacked up without degrading the characteristics of a semiconductor integrated circuit.
Furthermore, the CMP method has largely changed the structure of a via (which is also designated as a contact). A via herein means an interconnection for connecting a wire disposed on a predetermined layer with another wire disposed on another layer at the same potential when an arbitrary net (signal line), extends from the former layer to the latter layer at the different level.
FIG. 21 is a sectional view of an area where a via is formed. Conventionally, a via could connect merely the adjacent layers at the same potential. For example, an M1-M2 via 35 of FIG. 21 is a conventional via for connecting a first layer wire 31 with a second layer wire 32. Such a conventional via retains the wires at the same potential by allowing aluminum patterns of these wires to be directly in contact with each other. When the wire on the first layer is to be connected with a wire on the fourth layer at the same potential by utilizing such a conventional via, three vias, that is, the M1-M2 via 35 for connecting the first layer wire 31 and the second layer wire 32, an M2-M3 via 36 for connecting the second layer wire 32 and a third layer wire 33 and an M3-M4 via 37 for connecting the third layer wire 33 and a fourth layer wire 34, are disposed so as not to be stacked along one vertical line as is shown in FIG. 21. Accordingly, the connection between the first layer wire and the fourth layer wire at the same potential requires an area equal to the sizes of at least two vias.
As an improvement of this conventional via, a stacked via formed by the CMP method so as to be stacked along a vertical line (hereinafter referred to as the stacked via) as is shown in FIG. 22 has been proposed. In this stacked via, the wires to be connected, i.e., the first layer wire 31, the second layer wire 32, the third layer wire 33 and the fourth layer wire 34, are vertically stacked as shown in FIG. 22 with respectively providing plugs 40 between the first layer wire 31 and the second layer wire 32, between the second layer wire 32 and the third layer wire 33 and between the third layer wire 33 and the fourth layer wire 34. Thus, the first layer wire 31 is connected with the fourth layer wire 34. When this structure is adopted, the wires on arbitrary two layers can be connected by using an area equal to the size of one via. In FIG. 22, a reference numeral 38 denotes insulating layers included in the respective layers and a reference numeral 39 denotes a semiconductor substrate.
On the other hand, with regard to the routing technique, various methods have been proposed. Many of the conventionally proposed techniques are for the formation of the two-layer interconnection. However, the recent development of the LSI production technique can now realize a multilayer layout, and hence, a large number of proposes have recently been made on the multilayer interconnection.
Among these proposes, routing methods using via minimization technique are conspicuous. Examples of such methods include a Hsu method for the two-layer interconnection ("Minimum-Via Topological Routing", IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 235-246, 1983) and a Stallmann method for the multilayer interconnection using three or more layers ("Unconstrained Via Minimization for Topological Multilayer Routing", IEEE Trans, Computer-Aided Design, pp. 970-980, 1990). According to these routing methods, a routing pattern including a minimized number of vias can be generated. These routing methods are attained by perceiving that, when the number of vias is smaller, a routing pattern having a smaller routing area tends to be generated with ease. These methods further have a secondary effect to increase the yield in the production of semiconductor chips because of the decreased number of vias.
However, in these conventional routing methods utilizing the via minimization technique, an attention is paid to the minimization of the stacked vias alone. Therefore, for example, since the number of the stacked vias is decreased, the resultant routing pattern is bent, resulting in a disadvantage that the routing area can be accordingly enlarged. Furthermore, in the conventional routing methods utilizing the via minimization technique, routing topology including a minimized number of vias is generated on the assumption that the sizes of a line width and a via are "0". After this, an art work process is conducted for fleshing out the routing pattern and the vias (actual route patterning), so as to complete the routing. Accordingly, even though each wire or the like has actually its own size, the final routing area is ignored in the step of obtaining the routing topology. As a result, when the art work process is conducted, the wire density of the actual routing pattern is unexpectantly low, and the routing area is disadvantageously enlarged.